Skew-Tolerant Circuit DesignElsevier, 16 de jun. de 2000 - 300 páginas As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
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De dentro do livro
Resultados 1-5 de 44
... Sequencing Overhead in a Static ASIC 23 1.5.2 Sequencing Overhead in the Alpha 21164 24 1.5.3 Timing Analysis with Clock Skew 24 A Look Ahead 27 Exercises 29 Static Circuits 35 Preliminaries 36 2.1.1 Purpose of Memory Elements 36 2.1.2 ...
... sequencing overhead consumes an increasing fraction of the clock period. Engineers allocate ever more effort and chip routing resources to the clock network, yet clock skew is becoming a more serious concern. Systems using static logic ...
... sequencing overhead." In the next section, we will examine trends in system objectives that show sequencing overhead makes up an increasing portion of each cycle. Throughput and Laterncy Trends Designers judge their circuit performance ...
... overhead. We will then look at the trends in cycle time and find that the impact of overhead is becoming more severe ... sequencing overhead: T = #. *. overhead (1.3) The latency of the computation is the sum of the 1 Introduction.
... overhead of all N stages: latency = NT = X+ N • overhead (1.4) Equations 1.3 and 1.4 show how the impact of a fixed ... sequencing overhead if the cycle time T is 40 FO4 delays? 24 FO4 delays? 16 TFO4 delays? 12 FO4 delays? SOLUTION The ...
Conteúdo
1 | |
35 | |
Chapter 3 Domino Circuits | 67 |
Chapter 4 Circuit Methodology | 103 |
Chapter 5 Clocking | 143 |
Chapter 6 Timing Analysis | 161 |
Chapter 7 Conclusions | 193 |
Timing Constraints | 199 |
Solutions to EvenNumbered Exercises | 203 |
Bibliography | 211 |
Index | 219 |
About the Author | 224 |