Skew-Tolerant Circuit DesignElsevier, 16 de jun. de 2000 - 300 páginas As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
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... scan techniques can serve both latches and skew-tolerant domino in a simple and elegant way. None of these skew-tolerant circuit techniques would be practical if providing the necessary clocks introduced more skew than the techniques ...
... scan) in the E performance level driving a load of four standard loads. Extract the maximum setup time and clockto-Q (i.e., E-L2) delays from the data sheet assuming worst-case process and environment. 1.7 You are building the Motoroil ...
... Scan-in |A -: 107 == 107 1,107 L2 +L2 output (in phase with respect to input) | - - - LSSD Latch L1 Truth Table LSSD Latch L2 Truth Table B 0.444 0.444 0.454 |c 0.435 0.445 0.435 Inputs s: Inputs output D 0.967 0.968 - 0.967 c D E | L1 ...
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Conteúdo
1 | |
35 | |
Chapter 3 Domino Circuits | 67 |
Chapter 4 Circuit Methodology | 103 |
Chapter 5 Clocking | 143 |
Chapter 6 Timing Analysis | 161 |
Chapter 7 Conclusions | 193 |
Timing Constraints | 199 |
Solutions to EvenNumbered Exercises | 203 |
Bibliography | 211 |
Index | 219 |
About the Author | 224 |