Skew-Tolerant Circuit DesignElsevier, 16 de jun. de 2000 - 300 páginas As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
|
De dentro do livro
Resultados 1-5 de 85
... Clocks 125 4.1.6 Min-Delay Checks 125 Clocked Element Design 128 4.2.1 Latch Design 129 4.2.2 Domino Gate Design 1.31 4.2.3 Special Structures 132 Testability 133 4.3.1 Static Logic 134 4.3.2 Domino Logic 135 Historical Perspective 138 ...
... clock skew and to permit time borrow to balance logic between cycles. Skew-tolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead. My goal in writing this ...
... logic. Unfortunately, static CMOS logic is inadequate to meet timing objectives of the highest-performance systems ... clocks and eliminating latches, we find that skew-tolerant domino circuits eliminate all of the overhead. Three case ...
... logic when used properly. There have been a host of proposed latch designs; we evaluate many of the designs and conclude ... clock waveforms. Chapter 5 explores methods of generating and distributing clocks suitable for skew-tolerant ...
... logic, A.? If the cycle time is T', we see that the time available for logic is the cycle time minus the clock-to-Q delay and setup time: Alogic – T. - Aco- Apc (1.1) Unfortunately, real systems have imperfect clocks. On account of ...
Conteúdo
1 | |
35 | |
Chapter 3 Domino Circuits | 67 |
Chapter 4 Circuit Methodology | 103 |
Chapter 5 Clocking | 143 |
Chapter 6 Timing Analysis | 161 |
Chapter 7 Conclusions | 193 |
Timing Constraints | 199 |
Solutions to EvenNumbered Exercises | 203 |
Bibliography | 211 |
Index | 219 |
About the Author | 224 |