Skew-Tolerant Circuit DesignElsevier, 16 de jun. de 2000 - 300 páginas As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
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Resultados 1-5 de 49
... Gate Operation 15 1.4.2 Traditional Domino Clocking 18 1.4.3 Skew-Tolerant Domino 20 Case Studies 22 1.5.1 ... Delay 46 Memory Element Design 51 2.3.1 Transparent Latches 52 2.3.2 Pulsed Latches 55 2.3.3 Flip-Flops 57 Chapter 3 3.1 3.2 ...
... Delay Constraints 75 3.1.6 Recommendations and Design Issues 77 Domino Gate Design 79 3.2.1 Monotonicity and Dual-Rail Domino 79 3.2.2 Footed and Unfooted Gates 81 3.2.3 Keeper Design 84 3.2.4 Robustness Issues 85 Historical Perspective ...
... gate delay unused at the end of each cycle or half-cycle represents a greater wasted portion of the cycle as the number of gate delays per cycle decreases. All considered, the overhead of traditional domino pipelines can exceed 25% of ...
... delays, it is often beneficial to use a process-independent unit of delay so that intuition about delay can be ... gate delays per cycle and thus required more careful engineering. The fanout-of-4 inverter is particularly well suited to ...
... delays. Suppose the clock skew (tskew) is 2 FO4 inverter delays. What percentage of the cycle is wasted by ... gate delays per cycle. To evaluate the importance of sequencing overhead, we must tease apart these elements 1.2 Throughput ...
Conteúdo
1 | |
35 | |
Chapter 3 Domino Circuits | 67 |
Chapter 4 Circuit Methodology | 103 |
Chapter 5 Clocking | 143 |
Chapter 6 Timing Analysis | 161 |
Chapter 7 Conclusions | 193 |
Timing Constraints | 199 |
Solutions to EvenNumbered Exercises | 203 |
Bibliography | 211 |
Index | 219 |
About the Author | 224 |