Skew-Tolerant Circuit DesignElsevier, 16 de jun. de 2000 - 300 páginas As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
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... critical path, hiding the overhead and offering significant performance improvement. In this chapter, we begin by examining conventional systems built from flip-flops. We see how these systems have overhead that eats into the time ...
... critical paths in subsequent revisions on the same process and jumps as the chip is compacted to a new process that requires retuning. Overall, the number of FO4 delays per cycle has decreased at 12% per year. Putting everything ...
... critical paths. Several approaches could have eased the design. The most effective would have been to use latches rather than flip-flops on the critical paths. This would have removed clock skew from the cycle time budget, relinquishing ...
... critical rings entirely in domino for maximum performance. It describes the use of timing types to verify proper ... path. By considering the components of clock skew and dividing a large die into multiple clock domains, we can budget smaller ...
... critical paths involving domino or flip-flops, those paths will limit cycle time and the margin in the transparent latch blocks will go unused. It is much better to add margin only for 42 2 Static Circuits.
Conteúdo
1 | |
35 | |
Chapter 3 Domino Circuits | 67 |
Chapter 4 Circuit Methodology | 103 |
Chapter 5 Clocking | 143 |
Chapter 6 Timing Analysis | 161 |
Chapter 7 Conclusions | 193 |
Timing Constraints | 199 |
Solutions to EvenNumbered Exercises | 203 |
Bibliography | 211 |
Index | 219 |
About the Author | 224 |