Digital Design and FabricationVojin G. Oklobdzija CRC Press, 19 de dez. de 2017 - 656 páginas In response to tremendous growth and new technologies in the semiconductor industry, this volume is organized into five, information-rich sections. Digital Design and Fabrication surveys the latest advances in computer architecture and design as well as the technologies used to manufacture and test them. Featuring contributions from leading experts, the book also includes a new section on memory and storage in addition to a new chapter on nonvolatile memory technologies. Developing advanced concepts, this sharply focused book—
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Página xvi
... Combinational CMOS Digital Circuits Hendrawan Soeleman and Kaushik Roy ........ 19-1 20 xvii SECTION V Testing and Design for Testability 21 System. Clock - Powered CMOS for Energy - Efficient Computing Nestoras Tzartzanis and William ...
... Combinational CMOS Digital Circuits Hendrawan Soeleman and Kaushik Roy ........ 19-1 20 xvii SECTION V Testing and Design for Testability 21 System. Clock - Powered CMOS for Energy - Efficient Computing Nestoras Tzartzanis and William ...
Página 2-2
... combinational and sequential logic circuits . Combinational circuits produce outputs which are dependent on inputs only . There is no memory or feedback in the circuit . Circuits with feedback whose outputs depend on the inputs as well ...
... combinational and sequential logic circuits . Combinational circuits produce outputs which are dependent on inputs only . There is no memory or feedback in the circuit . Circuits with feedback whose outputs depend on the inputs as well ...
Página 2-3
... Combinational Circuits Any Boolean function , whether simple or complex , depending on the input combinations can have only two possible output values , a logic high or a logic low . Therefore , to construct a logic circuit that ...
... Combinational Circuits Any Boolean function , whether simple or complex , depending on the input combinations can have only two possible output values , a logic high or a logic low . Therefore , to construct a logic circuit that ...
Página 2-7
... combinational logic functions can be implemented with minimal number of transistors. This results in reduced parasitic capacitance and hence faster circuits. As a pass transistor design example, Fig. 2.12 shows a Boolean function unit ...
... combinational logic functions can be implemented with minimal number of transistors. This results in reduced parasitic capacitance and hence faster circuits. As a pass transistor design example, Fig. 2.12 shows a Boolean function unit ...
Página 2-8
... combinational logic circuits, the outputs are a logic combination of the current input signals. In sequential logic circuits the outputs depend not only on the current values of the inputs, but also on the preceding input values ...
... combinational logic circuits, the outputs are a logic combination of the current input signals. In sequential logic circuits the outputs depend not only on the current values of the inputs, but also on the preceding input values ...
Conteúdo
1-1 | |
2-1 | |
Chapter 3 HighSpeed LowPower Emitter Coupled Logic Circuits | 2-77 |
Chapter 4 PricePerformance of Computer Technology | 4-1 |
Memory and Storage | 4-21 |
Chapter 5 Semiconductor Memory Circuits | 5-1 |
Chapter 6 Semiconductor Storage Devices in Computing and Consumer Applications | 6-1 |
Design Techniques | 6-19 |
Chapter 14 Techniques for Leakage Power Reduction | 14-1 |
Chapter 15 Dynamic Voltage Scaling | 15-1 |
Chapter 16 Lightweight Embedded Systems | 16-1 |
Chapter 17 LowPower Design of Systems on Chip | 17-1 |
Chapter 18 ImplementationLevel Impact on LowPower Design | 18-1 |
Chapter 19 Accurate Power Estimation of Combinational CMOS Digital Circuits | 19-1 |
Chapter 20 ClockPowered CMOS for EnergyEfficient Computing | 20-1 |
Testing and Design for Testability | 20-27 |
Chapter 7 Timing and Clocking | 7-1 |
Chapter 8 MultipleValued Logic Circuits | 8-1 |
Chapter 9 FPGAs for Rapid Prototyping | 9-1 |
Chapter 10 Issues in HighFrequency Processor Design | 10-1 |
Chapter 11 Computer Arithmetic | 11-1 |
Design for Low Power | 11-39 |
Chapter 12 Design for Low Power | 12-1 |
Chapter 13 LowPower Circuit Technologies | 13-1 |
Current Practices and Challenges for Tomorrow | 21-1 |
Chapter 22 Test Technology for Sequential Circuits | 22-1 |
Chapter 23 Scan Testing | 23-1 |
Chapter 24 ComputerAided Analysis and Forecast of Integrated Circuit Yield | 24-1 |
Index | 24-27 |
Back cover | 24-43 |
Termos e frases comuns
active adder addition algorithm applications approach architecture becomes bit line block capacitance cards carry cell charge chip circuit clock CMOS combinational compared complexity Computer connected consumption converter core critical cycle delay depending devices distribution drain drives dynamic effect embedded energy example fault FIGURE Flash flip-flop frequency function gate given IEEE implementation improve increase input integrated internal inverter jitter latch layer leakage limit load logic loop memory mode multiplier NMOS node noise operation optimization output path performance phase possible problem processor pulse realized reduced reference scaling scan selected shown in Fig shows signal simulation speed stage standard static structure substrate supply voltage switching synthesis Table techniques threshold transistor typically VLSI voltage yield
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Página 8-24 - This research was supported in part by grants from the National Science Foundation (GS-32065) and the Spencer Foundation.
Página 1-28 - Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions,
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